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IS31IO7328 integrated silicon solution, inc. ? www.issi.com 1 rev.a, 12/27/2011 multi-function i/o driver january 2012 general description the IS31IO7328 2-wire serial-interfaced peripheral features 8 i/o ports. ports are divided into four push pull i/os and four open-drain i/os and transition detection. any of the 8 i/o ports can be configured as an input or an output. all i/o ports configured as inputs are continuously monitored for state changes (transition detection). state changes are indicated by the int _______ output. the interrupt is latched, allowing detection of transient changes. when the IS31IO7328 is subsequently read through the serial interface, any pending interrupt is cleared. the open-drain outputs are rated to sink 20ma at 0.22v headroom, and are capable of driving leds. the rst ________ input clears the serial interface, terminating any i 2 c communication to or from the IS31IO7328. the IS31IO7328 uses two address inputs to allow 2 i 2 c slave addresses. the slave address also determines the power-up logic state for the i/o ports. features ? 400khz i 2 c serial interface ? 2.4v to 5.5v operation ? 4 push-pull i/o ports ? 4 open-drain i/o ports, rated to 20ma sink current at 0.22v headroom ? selectable i/o port power-up default logic states ? int _______ output alerts change on inputs ? low 0.3 a (typ.) standby current ? -40c to +125c temperature range applications ? cell phones ? notebooks ? san/nas ? satellite radio ? servers ? automotive typical application circuit figure 1 typical application circuit
IS31IO7328 integrated silicon solution, inc. ? www.issi.com 2 rev.a, 12/27/2011 input filter i2c control power-on reset i/o ports int od3 od2 od1 od0 pp3 pp2 pp1 pp0 ad scl sda rst figure 2 functional block diagram copyright ? ? ? 2011 ? integrated ? silicon ? solution, ? inc. ? all ? rights ? reserved. ? issi ? reserves ? the ? right ? to ? make ? changes ? to ? this ? specification ? and ? its ? products ? at ? any ? time ? without ? notice. ? issi ? assumes ? no ? liability ? arising ? out ? of ? the ? application ? or ? use ? of ? any ? information, ? products ? or ? services ? described ? herein. ? customers ? are ? advised ? to ? obtain ? the ? latest ? version ? of ? this ? device ? specification ? before ? relying ? on ? any ? published ? information ? and ? before ? placing ? orders ? for ? products. ? integrated ? silicon ? solution, ? inc. ? does ? not ? recommend ? the ? use ? of ? any ? of ? its ? products ? in ? life ? support ? applications ? where ? the ? failure ? or ? malfunction ? of ? the ? product ? can ? reasonably ? be ? expected ? to ? cause ? failure ? of ? the ? life ? support ? system ? or ? to ? significantly ? affect ? its ? safety ? or ? effectiveness. ? products ? are ? not ? authorized ? for ? use ? in ? such ? applications ? unless ? integrated ? silicon ? solution, ? inc. ? receives ? written ? assurance ? to ? its ? satisfaction, ? that: ? a.) ? the ? risk ? of ? injury ? or ? damage ? has ? been ? minimized; ? b.) ? the ? user ? assume ? all ? such ? risks; ? and ? c.) ? potential ? liability ? of ? integrated ? silicon ? solution, ? inc ? is ? adequately ? protected ? under ? the ? circumstances
IS31IO7328 integrated silicon solution, inc. ? www.issi.com 3 rev.a, 12/27/2011 pin configuration package pin configuration (top view) qfn-16 1 2 3 4 12 11 10 9 ad rst int vcc pp2 pp1 pp0 od3 pin description no. pin description 1 ad address inputs. select device slave address with ad. 2 rst ________ reset input, active low. drive rst _________ low to clear the 2-wire interface. 3 int _______ interrupt output, active low. int _______ is an open-drain output. 4 vcc positive supply voltage. bypass v dd to gnd with a ceramic capacitor of at least 1 f. 5,14 gnd ground. 6~9 od0~od3 open-drain i/o ports. 10~13 pp0~pp3 cmos push-pull i/o ports. 15 scl i 2 c-compatible serial-clock input. 16 sda i 2 c-compatible serial-data i/o. thermal pad connect to gnd.
IS31IO7328 integrated silicon solution, inc. ? www.issi.com 4 rev.a, 12/27/2011 ordering information industrial range: -40c to +125c order part no. package qty/reel IS31IO7328-qfls4-tr qfn-16, lead-free 2500
IS31IO7328 integrated silicon solution, inc. ? www.issi.com 5 rev.a, 12/27/2011 absolute maximum ratings supply voltage, v cc -0.3v ~ +6.0v voltage at any input pin -0.3v ~ v cc +0.3v scl, sda, ad, rst ________ , int _______ , od0-od3 -0.3v ~ +6.0v pp0?pp3 -0.3v ~ v cc +0.3v pp source output current 100ma pp/od sink current 120ma sda sink current 10ma int _______ sink current 10ma continuous power dissipation (t a = 70c) 16-pin wqfn (derate 29.0mw/c over 70c) 2.32w maximum junction temperature, t jmax 150c storage temperature range, t stg -65c ~ +150c operating temperature range, t a ? 40c ~ +125c solder information, vapor phase (60s) infrared (15s) 215c 220c note: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the sp ecifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics t a = 25c, v cc = 2.4v ~ 5.5v, unless otherwise noted. typical values are at v cc = 3.3v, t a = 25c. (note 1) symbol parameter condition min. typ. max. unit v cc supply voltage 2.4 5.5 v v por power-on-reset voltage v cc falling, t a = -40c 2.35 v v cc falling, t a = -20c 2.3 i stb standby current (interface idle) scl and sda and other digital inputs at v cc 0.3 1.9 a i+ supply current (interface running) f scl = 400khz; other digital inputs at v cc 8 20 a v ih input high-voltage, sda, scl, ad rst ________ , od0~od3, 1.4 v v il input low-voltage, sda, scl, ad rst ________ , od0~od3, 0.4 v i ih , i il input leakage current, sda, scl, ad rst ________ , od0~od3, pp0~pp3 sda, scl, ad, rst ________ , od0~od3, pp0~pp3 at v dd or gnd. -0.2 +0.2 a c in input capacitance, sda, scl, ad, rst ________ , od0~od3, pp0~pp3 (note3) 10 pf v ol output low voltage, pp0~pp3, od0~od3 v cc = 2.5v, i sink = 10ma 200 mv v cc = 3.3v, i sink = 15ma 240 v cc = 5.0v, i sink = 20ma 250 v oh output high voltage pp0~pp3 v cc = 2.5v, i source = 5ma v cc -316 mv v cc = 3.3v, i source = 5ma v cc -213 v cc = 5.0v, i source = 10ma v cc -289 v olsda output low-voltage sda i sink = 6ma 180 mv v ol int _______ output low-voltage int _______ i sink = 5ma 180 mv
IS31IO7328 integrated silicon solution, inc. ? www.issi.com 6 rev.a, 12/27/2011 timing characteristics v cc = 2.4v ~ 5.5v, unless otherwise noted. typical values are at v cc = 3.3v, t a = 25c. (note 3) symbol parameter condition min. typ. max. unit f scl serial-clock frequency 400 khz t buf bus free time between a stop and a start condition 1.3 s t hd, sta hold time (repeated) start condition 0.6 s t su, sta repeated start condition setup time 0.6 s t su, sto stop condition setup time 0.6 s t hd, dat data hold time 0.9 s t su, dat data setup time 100 ns t low scl clock low period 1.3 s t high scl clock high period 0.7 s t r rise time of both sda and scl signals, receiving (note 4) 20 + 0.1cb 300 ns t f fall time of both sda and scl signals, receiving (note 4) 20 + 0.1cb 300 ns t f, t x fall time of sda transmitting (note 4) 20 + 0.1cb 250 ns t sp pulse width of spike suppressed (note 5) 50 ns c b capacitive load for each bus line 400 pf t w rst ________ pulse width 500 ns t rst _______ rst ________ rising to start condition setup time 1 s port and interrupt i n t _______ timing characteristic v dd = 2.4v ~ 5.5v, unless otherwise noted. typical values are at v dd = 3.3v, t a = 25c. (note 3) parameter symbol condition min. typ. max. unit port output data valid t pv c l 100pf 4 s port input setup time t psu c l 100pf 0 s port input hold time t ph c l 100pf 4 s int ???? input data valid time t iv c l 100pf 4 s int ???? reset delay time from acknowledge t ir c l 100pf 4 s note 1: all parameters are tested at ta = 25c. specifications over temperature are guaranteed by design. note 2: a master device must provide a hold time of at least 300ns for the sda signal (referred to vil of the scl signal) in order to bridge the undefined region of scl?s falling edge. note 3: guaranteed by design. note 4: cb = total capacitance of one bus line in pf. isink 6ma. tr and tf measured between 0.3 v cc and 0.7 v cc . note 5: input filters on the sda and scl inputs suppress noise spikes less than 50ns.
IS31IO7328 integrated silicon solution, inc. ? www.issi.com 7 rev.a, 12/27/2011 table 1 power up default state for i/o ports pin connection port power up default ad pp3 pp2 pp1 pp0 od3 od2 od1 od0 ad = gnd 0 0 0 0 0 0 0 0 ad = v dd 1 1 1 1 hi-z hi-z hi-z hi-z table 2 command byte register command byte address function power-up default protocol 00h (note 6) input port a (od0~od3) xxxx r 01h (note 6) input port b (pp0~pp3) xxxx r 02h (note 6) output port a refer to table 1 r/w 03h (note 6) output port b refer to table 1 r/w 04h (note 6,7) port a configuration 0000 r/w 05h (note 6,7) port b configuration 0000 r/w 06h (note 6) port a interrupt control 0000 r/w 07h (note 6) port b interrupt control 0000 r/w note 6: when reading or writing data from/to the port a/b, the 4 msbs of the data are effective note 7: when configuring the command byte registers with address 04 or 05, the lsbs of data have to be set to 0.
IS31IO7328 integrated silicon solution, inc. ? www.issi.com 8 rev.a, 12/27/2011 figure 3 2-wire serial interface timing details figure 4 start and stop conditions figure 5 bit transfer
IS31IO7328 integrated silicon solution, inc. ? www.issi.com 9 rev.a, 12/27/2011 detailed description functional overview the IS31IO7328 is a multi-function i/o driver operating from a 2.4v to 5.5v supply with four push-pull and four open-drain i/o ports. each open-drain and push-pull port is rated to sink 20ma at 0.22v headroom, and the entire device is rated to sink 160ma at 0.22v headroom into all ports combined. the outputs drive loads connected to supplies up to +5.5v. the IS31IO7328 is set to two i 2 c slave addresses using the address select inputs ad, and is accessed over an i 2 c serial interface up to 400 khz. the rst ________ input clears the serial interface in case of a bus lockup, terminating any serial transaction to or from the IS31IO7328. the IS31IO7328 consists of input, output port registers, configuration registers and interrupt control register. all i/o ports offer latching transition detection when configured as inputs. all input ports are continuously monitored for changes. a latching interrupt output, int _______ , is programmed to flag logic changes on ports used as inputs. data changes on any input port forces int _______ to a logic-low. changing the i/o port level through the serial interface does not cause an interrupt. the interrupt output int _______ is cleared successfully by reading the corresponding input/output ports. ports default to logic-high or logic-low on power-up in groups of two (see table 1). initial power-up on power-up, the transition detection logic is reset, and int _______ is reset. the power-up default states of the 8 i/o ports are set according to the i2c slave address selection inputs, ad (see table 1). for i/o ports used as inputs, ensure that the default states are logic-high so that the i/o ports power up in the high impedance state. power-on reset the IS31IO7328 contains an integral power-on-reset (por) circuit that ensures all registers are reset to a known state on power-up. when v dd rises above v por (2.3v max), the por circuit releases the registers and 2-wire interface for normal operation. when v dd drops to less than v por , the IS31IO7328 resets all register contents to the por defaults. rst ________ input the active-low rst ________ input voids any i2c transaction involving the IS31IO7328, forcing the IS31IO7328 into the i2c stop condition. a reset does not affect the interrupt output. standby mode when the serial interface is idle, the IS31IO7328 automatically enters standby mode, drawing minimal supply current. i/o port input transition detection all i/o ports configured as inputs are monitored for changes since the expander was last accessed through the serial interface. the open-drain interrupt output, int _______ , activates when one of the port pins changes states and only when the pin is configured as an input. the interrupt deactivates when the input/output register is read. a pin configured as an output does not cause an interrupt. each 8-bit port register is read independently; therefore, an interrupt caused by port a (od0~od3) is not cleared by a read of port b (pp0~pp3)?s register. changing an i/o from an output to an input may cause a false interrupt to occur if the state of that i/o does not match the content of output port register. the IS31IO7328 has interrupt control register to avoid false interrupt by setting the interrupt control register bit high firstly, when the i/o state is stable, clear the interrupt control register to enable the input transition detection function. accessing the IS31IO7328 serial addressing the IS31IO7328 operates as a slave that sends and receives data through a 2-wire interface. the interface uses a serial data line (sda) and a serial clock line (scl) to achieve bidirectional communication between master(s) and slave(s). a master, typically a microcontroller, initiates all data transfers to and from the IS31IO7328, and generates the scl clock that synchronizes the data transfer (see figure 3). sda operates as both an input and an open-drain output. a pull up resistor, typically 4.7k ? , is required on sda. scl operates only as an input. a pull up resistor, typically 4.7k ? , is required on scl if there are multiple masters on the 2-wire interface, or if the master in a single-master system has an open-drain scl output. each transmission consists of a start condition sent by a master, followed by the IS31IO7328?s 7-bit slave addresses plus r/w bits, 1 or more data bytes, and finally a stop condition (see figure 4).
IS31IO7328 integrated silicon solution, inc. ? www.issi.com 10 rev.a, 12/27/2011 start and stop conditions both scl and sda remain high when the interface is not busy. a master signals the beginning of a transmission with a start (s) condition by transitioning sda from high to low while scl is high. when the master has finished communicating with the slave, the master issues a stop (p) condition by transitioning sda from low to high while scl is high. the bus is then free for another transmission (see figure 4). bit transfer one data bit is transferred during each clock pulse. the data on sda must remain stable while scl is high (figure 5). figure 6 acknowledge 12345678 12345678 12345678 scl start condition r/w acknowledge from slave acknowledge from slave acknowledge from slave slave address 0 command byte data nibble 0 0 0 0 sda internal write to port data out from port t pv data valid s a a a write 0 when writing the port figure 7 writing to the IS31IO7328 12345678 12345678 acknowledge from sn7328 1 s ana 101 1 0ad0 d7 d6 d5 d4 d3 d2 d1 d0 no acknowledge from master p port i/o ineffective data 12345678 12345678 scl acknowledge from sn7328 0 sa a 101 1 0ad0 command byte acknowledge from sn7328 w t iv port int output r s=start condition p=stop condition shaded=slave transmission na=no acknoledge t psu t ir t ph sda effective data figure 8 reading i/o ports of IS31IO7328 note: data from/to IS31IO7328, only the 4 msbs of the data are effective
IS31IO7328 integrated silicon solution, inc. ? www.issi.com 11 rev.a, 12/27/2011 slave address the IS31IO7328 has a 7-bit slave address. the 8th bit following the 7-bit slave address is the r/w ____ bit. set this bit low for a write command and high for a read command. the complete slave address is: a6 a5 a4 a3 a2 a1 a0 1 0 1 1 0 ad 0 data bus transaction the command byte is the firs t byte to follow the 8-bit device slave address during a write transmission (see table 2). the command byte is used to determine which of the following registers are written or read. acknowledge the acknowledge bit is a clocked 9th bit the recipient uses to acknowledge receipt of each byte of data (see figure 6). each byte transferred effectively requires 9bits. the master generates the 9th clock pulse, and the recipient pulls down sda during the acknowledge clock pulse, such that the sda line is stable low during the high period of the clock pulse. when the master is transmitting to the IS31IO7328, the device generates the acknowledge bit because the IS31IO7328 is the recipient. when the IS31IO7328 is transmitting to the master, the master generates the acknowledge bit because the master is the recipient. configuration registers the configuration registers configure the directions of the i/o pins. set the bit in the respective configuration register to enable the corresponding port as an input. clear the bit in the configuration register to enable the corresponding port as an output. the 4 lsbs of the commend data should be set to 0. interrupt control registers the interrupt control registers control the interrupt function of i/o ports when the i/o port used as input. set the bit in the respective interrupt control register to disable the corresponding port?s interrupt function. clear the bit in the interrupt control register to enable the corresponding port?s interrupt function. writing to port registers transmit data to the IS31IO7328 by sending the device slave address and setting the lsb to a logic zero. the command byte is sent after the address and determines which registers receive the data following the command byte. a write to either output port groups of the IS31IO7328 starts with the master transmitting the group?s slave address with the r/w ____ bit set low. the master can now transmit one or more bytes of data. the IS31IO7328 acknowledges these subsequent bytes of data and updates the corresponding group?s ports with each new byte until the master issues a stop condition (figure 7). reading port registers to read the device data, the bus master must first send the IS31IO7328 address with the r/w ____ bit set to zero, followed by the command byte, which determines which register is accessed. after a restart, the bus master must then send the IS31IO7328 address with the r/w ____ bit set to 1. data from the register defined by the command byte is then sent from the IS31IO7328 to the master. the IS31IO7328 acknowledges the slave address, and samples the ports during the acknowledge bit. int _______ desserts during the slave address acknowledge. when the master reads one byte from the i/o ports of the IS31IO7328 and subsequently issues a stop condition (figure 8), the IS31IO7328 transmits the current port data, clears the change flags, and resets the transition detection. int _______ desserts during the slave acknowledge. the new snapshot data is the current port data transmitted to the master, and therefore, port changes occurring during the transmission are detected. port output signal-level translation the open-drain output architecture allows for level translation to higher or lower voltages than the IS31IO7328?s supply. each of the push-pull output ports has protection diodes to v+ and gnd. when a port output is driven to a voltage higher than v+ or lower than gnd, the appropriate protection diode clamps the output to a diode drop above v+ or below gnd. when the IS31IO7328 is powered down (v+ = 0v), every output port?s protection diodes to v+ and gnd continue to appear as a diode clamp from each output to gnd (figure 9). each of the i/o ports od0~od3 has a protection diode to gnd (figure 10). when a port is driven to a voltage lower than gnd, the protection diode clamps the port to a diode drop below gnd. to obtain a high voltage, open-drain i/o ports should connect an resistance to v dd (figure 10). figure 9 IS31IO7328 push-pull i/o ports structure
IS31IO7328 integrated silicon solution, inc. ? www.issi.com 12 rev.a, 12/27/2011 figure 10 IS31IO7328 open-drain i/o ports structure driving leds in the case that an od output is used to drive an led, a 100k ? pull-up resistor should be used to prevent the output from floating while the led is off. an od port which is left floating may experience a slight increase in input leakage current due to the input structure of the io port. IS31IO7328 vdd od0 od1 od2 od3 vcc 100k figure 11 driving leds with od ports
IS31IO7328 integrated silicon solution, inc. ? www.issi.com 13 rev.a, 12/27/2011 classification reflow profiles profile feature pb-free assembly preheat & soak temperature min (tsmin) temperature max (tsmax) time (tsmin to tsmax) (ts) 150c 200c 60-120 seconds average ramp-up rate (tsmax to tp) 3c/second max. liquidous temperature (tl) time at liquidous (tl) 217c 60-150 seconds peak package body temperature (tp)* max 260c time (tp)** within 5c of the specified classification temperature (tc) max 30 seconds average ramp-down rate (tp to tsmax) 6c/second max. time 25c to peak temperature 8 minutes max. figure 12 classification profile
IS31IO7328 integrated silicon solution, inc. ? www.issi.com 14 rev.a, 12/27/2011 tape and reel information
IS31IO7328 integrated silicon solution, inc. ? www.issi.com 15 rev.a, 12/27/2011 package information qfn-16 note: all dimensions in millimeters unless otherwise stated.

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